Layout vs Schematic and Parasitic Extraction Engineer in Albany, NY at IBM

Date Posted: 8/6/2018

Job Snapshot

  • Employee Type:
    Full-Time
  • Location:
    Albany, NY
  • Job Type:
  • Experience:
    Not Specified
  • Date Posted:
    8/6/2018

Job Description

Job Title: Layout vs Schematic (LVS) and Parasitic Extraction Engineer
Preferred Locations: (Austin, TX, Cambridge, MA, Albany, NY, San Jose, CA and Yorktown, NY)

Be part of a dynamic and skilled IBM Research team developing design enablement for the world's most advanced semiconductor technologies. Develop Layout vs Schematic (LVS) and Parasitic Extraction (PEX) decks using industry-standard tools such as Mentor Graphics’ Calibre and Synopsys Star-RCXT. Close and frequent cooperation with process development engineers will be required.

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